❯ Samsung plans to use TSMC’s 3nm process for NVHBM base dies as Nvidia seeks a common design across memory suppliers

Rivals share a manufacturing chainReuters, citing the Seoul Economic Daily, reports that Samsung has accepted Nvidia’s requirement to use TSMC’s 3nm process for the base dies of custom NVHBM. The newspaper, citing industry sources, says Nvidia made the same request to SK Hynix and Micron. The supply arrangement remains a media report.

The controller moves into the memory stackHigh-bandwidth memory, or HBM, supplies data rapidly to AI processors. In its August technical introduction, Nvidia explains that NVHBM places a custom memory controller in the base die beneath the stack, freeing area on the main compute chip. The design aims to improve data movement, power use and the allocation of chip area.

This order has a specific scopeThe report says Samsung plans to retain its internal production approach for standard HBM and custom products for other customers. The arrangement concerns the base die rather than the entire memory product. The stacked memory and the logic chip beneath it perform different functions, allowing their manufacturing responsibilities to be allocated separately.

Common implementations can simplify integrationNvidia aims to standardize implementations across memory suppliers, reducing the integration and validation involved in changing sources. That could simplify custom-chip development for AI system builders. Memory companies would compete on their ability to deliver a platform customer’s specified architecture as well as capacity and bandwidth.

▮ SIGNALAI platform companies are extending their influence into memory design, creating manufacturing arrangements that bring direct competitors into the same product chain.