IT之家: Axelera AI unveils Titania AIPU architecture for data-center inference

IT之家 reported that Axelera AI unveiled the architecture of Titania, its third-generation AIPU chip, on Nov. 12 local time. The chip targets data-center inference and is slated for volume production in Q3 2027, with more than $300 million in orders already booked. Titania uses two compute chiplets based on Axelera’s third-generation D-IMC architecture, has a 400W design power, and delivers up to 2.5 PFLOPS in FP8. It also integrates 128GB of LPDDR6 memory.