❯ Positron Unveils Up to $875M in Funding to Bet on Memory-Efficient Inference

Parsing the TotalAI inference chipmaker Positron disclosed a Series C package of up to $875 million: roughly $375 million has closed, with an additional component of up to $500 million, at a post-money valuation of about $5 billion. NEA, Atreides, Valor and Andra were among the investors. Positron runs trained models on high-bandwidth, power-efficient inference hardware designed to reduce reliance on expensive advanced packaging and specialized high-bandwidth memory.

A One-Year LeapPositron previously raised roughly $230 million in Series B funding at a valuation above $1 billion. By September 2026, the new package had pushed that figure to about $5 billion. Crunchbase counts the $500 million component as this week’s round, but the company’s broader disclosure is larger, so closed capital and future capacity must be separated. As chat, search and enterprise-agent calls grow, buyers are turning from whether models can be trained to what each answer costs.

Memory FirstPositron is not cloning a training GPU. It designs around data movement and memory bottlenecks in inference and uses more readily available memory. The pitch centers on throughput, power and deployment cost for model providers and data centers. Avoiding a head-on training battle gives its focused architecture room against Nvidia, while concentrating risk in software compatibility, manufacturing and real-world workload performance. The round is principally about crossing that delivery threshold.

Budget SplitInference is becoming its own procurement category rather than a GPU add-on. Training silicon remains driven by peak performance; inference puts more weight on cost, electricity, memory capacity and predictable throughput, leaving room for specialized architectures. Positron’s $5 billion valuation assumes customers will switch hardware to lower per-query cost. The proof will be whether migration costs remain below the compute savings after volume production.

▪ SIGNALAs inference bills overtake training bills, chips optimized around memory, power and throughput can carve out a separate data-center budget.